High- κ van der Waals GaPS4 for hysteresis-free 2D electronics at the thermionic limit

The continued scaling of silicon-based transistors is increasingly constrained by severe short-channel effects. While high-mobility two-dimensional (2D) semiconductors offer a promising post-silicon pathway, their performance is fundamentally limited by the lack of high-dielectric-constant (high-κ) insulators capable of forming atomically smooth, defect-free interfaces. Here, we report the facile synthesis and characterization of single-crystalline layered GaPS4 as a robust van der Waals (vdWs) high-k dielectric. The GaPS4 crystals exhibit high breakdown field strengths (Ebd) exceeding 10 MV/cm and low gate leakage currents on the order of 10−6 A/cm2. Enabled by the atomically sharp vdW interface and efficient electrostatic coupling, top-gated GaPS4/MoS2 field-effect transistors (FETs) achieve near-ideal gate control, characterized by a thermionic-limit-approaching subthreshold swing of 60 mV/dec and negligible hysteresis ∼6 mV at room temperature. Such FETs can be integrated into functional logic gates. This study establishes two-dimensional GaPS4 as a promising gate dielectric candidate for next-generation high-speed nanoelectronics.