A reconfigurable routing architecture of asynchronous NoC systems

Reconfigurable computing is pivotal for power-constrained industrial IoT edge devices requiring real-time hardware adaptation to dynamic workloads. However, conventional coarse-grained reconfigurable architectures (CGRAs) based on synchronous circuit suffer from prohibitive power overheads caused by global clock distribution and limited scalability due to timing closure constraints, thereby hindering efficient dynamic reconfiguration. In this paper, we propose an asynchronous mesh Network-on-Chip (NoC) that eliminates global clock synchronisation, enabling near-linear power scaling with network size. A dynamic path selection algorithm further optimises data routing based on real-time workload distribution, resulting in improved latency compared to static routing. Finally, we validate our proposed approach with a test chip fabricated in a 180 nm SMIC process, demonstrating an overall power consumption of only 5.27 mW and 0.08 mW per node within the network. Comparative analysis with existing work highlights the significant power efficiency advantage of our design.