Synthesis of stacked HSC-T using improved mixed frequency PWM

Need to address the topological and operational challenges of classical multilevel inverters (MLI) lead to the development of numerous symmetrical and Asymmetrical topologies of reduced switch count (RSC) MLI. Among, HSC and T-type offer simplified structures with appreciable reduction in switch count, however, their inability to support asymmetric ability with simplified PWM acts as a viable demerit. Though, Hybrid PWM is the popular mixed frequency scheme reported, its implementation on classical asymmetrical MLIs such as CHB produces sudden voltage spikes in output voltage, degrades the performance and, further not suitable to control RSC-MLI. To address the limitation, development of a simple and effective RSC-MLI with HSC integrated T-module is proposed with an improved mixed frequency PWM. The modified switching logic of the proposed PWM can realize asymmetrical cascaded RSC-MLI with clean output performance. The superiority of the developed topology and proposed PWM over the popular CHB in-terms of switch count, total standing voltage (TSV), switching losses, improved output performance and simplified implementation is demonstrated on simulation and obtained simulation results are validated on experimental environment with FPGA controller.