A scalable and adaptive cell-level mapping algorithm for QCA placement and routing

Quantum-dot Cellular Automata (QCA) represent an innovative nanoscale computing architecture, widely used for designing high-density and low-power circuits. Current QCA placement and routing (P&R) processes often depend on fixed clock schemes, where gate-level circuit layouts are generated using P&R algorithms. While previous efforts have enhanced the spatial resource utilisation of clock grids by increasing routing paths within grid cells, this approach has significantly complicated the mapping process from gate-level to cell-level. To address these challenges, this paper presents an adaptive mapping algorithm designed for arbitrary clock grids. By employing a heuristic approach, the algorithm effectively maps complex gate-level circuits to cell-level layouts, optimising cell distribution and signal routing while ensuring signal synchronisation and stability. The proposed algorithm not only improves layout efficiency but also demonstrates exceptional performance in the automated design of medium to large-scale QCA circuits.