Design and FPGA implementation of digital down converter using reversible adders

In the fields of quantum computing, nanotechnology and optical computing, reversible computing has become a highly attractive area of study. This paper presents the design and implementation of a field-programmable gate array (FPGA)-based digital down converter (DDC) using reversible adders for software-defined radio (SDR) applications. The DDC comprises a polyphase mixer followed by a cascaded integrator comb (CIC) filter and finally a lowpass finite impulse response (FIR) filter. The canonical implementation of the polyphase mixer reduces the multipliers. The polynomial-based CIC filter improves the passband characteristics. Again, the polyphase transposed FIR filter coefficients are represented in the canonical signed-digit (CSD) encoding technique. This process reduces the adders significantly. Each component of the DDC is implemented with reversible hybrid parallel prefix adders (RHPPAs). The presented RHPPA consists of reversible ripple carry adders (RRCAs), which consume less quantum cost compared to popular parallel adders. The proposed DDC is described with efficient coding in hardware description language (HDL) using the Xilinx Vivado 2024.1 and implemented on the Kintex-7 board. Synthesis results showed that each component of the DDC runs faster compared to its conventional structure at a marginal cost of area. Comparative analysis indicated that the proposed DDC using RHPPA has achieved significant improvement of area-delay product (ADP) by 15.59% and power-delay product (PDP) by 26.16% to the corresponding most recent architecture. Also, the design has achieved a high value of spurious-free dynamic range (SFDR), which is 116 dB.