Design and performance comparison of 6T, 8T and 11T SRAM cells using TSMC and UMC 65 nm CMOS technology

The growing demand for high-performance and energy-efficient memory has accelerated the development of low-power static random-access memory (SRAM) architectures, which form a critical component of modern system-on-chip (SoC) designs. This paper presents a comprehensive analysis of a novel 11T SRAM cell, with a strong emphasis on physical design considerations. The proposed 11T cell introduces a dedicated read line and a transmission gate in place of conventional pass transistors, resulting in enhanced read/write stability and reduced power consumption. The design is implemented and evaluated using Cadence Virtuoso with TSMC 65 nm CMOS technology. Simulation results confirm that the proposed 11T cell achieves 39.56% improved write static noise margin (SNM) and 11.50% lower power dissipation and 6.7% higher write speed compared to stack transistor-based 11T architecture. Additionally, a comparative analysis involving 6T, 8T, conventional 11T, and the proposed 11T SRAM cells was performed using both TSMC 65 nm and UMC 65 nm technology nodes. The results demonstrate that TSMC 65 nm technology yields superior performance over UMC. Post-layout simulations further validate the design’s stability in the presence of parasitic effects, with all evaluations conducted at a supply voltage of 1.2 V.