Low-power ternary full adder/subtractor design using GNRFET technology

Multi-valued logic (MVL) offers a promising alternative to binary logic, enhancing data processing efficiency within the same transistor constraints. Graphene nano-ribbon field effect transistors (GNRFETs) demonstrate strong potential for MVL applications due to their high operational frequency and unique electronic properties. In this work, we present the design and implementation of ternary full adder and full subtractor circuits optimised for arithmetic logic units (ALUs). Additionally, we redesigned comparable circuits using carbon nano-tube field effect transistors (CNTFETs) to evaluate performance differences. Our comparative analysis highlights distinct advantages and trade-offs between GNRFET and CNTFET architectures. GNRFET-based designs achieved a peak performance of 10 GHz, significantly surpassing the minimum operational frequency of 0.5 GHz observed in CNTFET-based counterparts. However, the power dissipation of GNRFET circuits was about 27% to 28.5% of that in CNTFET designs, while exhibiting about 158% decrease in processing speed. These findings underscore GNRFET’s viability for MVL applications, particularly in high-speed computational environments.