Metaheuristic-based Detection of Stuck-at Faults in Reversible Logic Using Horse Herd Optimization

Low-power circuit design has become a promising field for today’s technological era, particularly in reversible VLSI circuit design. Testing of VLSI circuits has become a tedious task using traditional testing techniques. Automatic test pattern generation generates the test sets that can find the faults present in the circuit, but this tool may not produce the complete test set to cover the entire fault set detection process. To overcome this, we use an optimization algorithm to generate the test vectors, which will overcome and satisfy many crucial parameters in the circuit testing design metrics, such as cost, time spent, fault coverage, and power consumption involved in the test set generation during the testing process. In this work, I have mainly concentrated on the generation of the minimal test vectors using an optimization algorithm with high fault coverage, and this feature deepens the experimental validation process and offers insightful information about how the optimized test pattern generation behaves in different fault scenarios.