FPGA Implementation for Computing Eigenvalues Utilizing the Parallel Jacobi Method with the CORDIC Algorithm

This paper presents a novel low-latency, reconfigurable algorithm for eigenvalue computation by integrating the parallel Jacobi method with a CORDIC-based hardware framework. Unlike conventional methods, the proposed approach uses shift–add CORDIC iterations to generate rotation parameters, reducing per-rotation latency and eliminating multipliers. The design supports real-symmetric, real skew-symmetric, complex Hermitian, and complex skew-Hermitian matrices, and can eliminate multiple off-diagonal elements in parallel for faster convergence. Hardware-aware optimizations enable efficient FPGA implementation, fully exploiting parallelism. The design is validated on a ZYBO Z7 FPGA operating at 160 MHz, achieving LUT utilization of 38.31%, 53.75%, and 61.18% with corresponding power consumption of 0.759, 3.083, and 3.4 W for matrix sizes of 4 × 4, 8 × 8, and 16 × 16, respectively. The proposed method offers a scalable, power-efficient, and FPGA-friendly eigenvalue solver suitable for real-time signal processing, image analysis, and direction-of-arrival estimation.