Low-thermal-stress fabrication process enabled by SD-2 borosilicate glass

Abstract Thermal stress generally exists in wafer-level silicon-on-glass (SOG) bonding devices, which significantly affects the stability of the devices. The thermal stress mainly originates from the temperature-dependent Young’s modulus of silicon and the mismatched coefficient of thermal expansion (CTE) between silicon and glass. This paper presents a novel SD-2 borosilicate glass-based wafer-level SOG fabrication process for reducing thermal stress, in which the SD-2 glass exhibits closer CTE alignment with silicon substrate than conventional Borofloat 33 (BF33) glass. The SOG bonding parameters between the SD-2 and silicon substrates are then characterized by theoretical analysis and experimental validation. Through well-designed contrast experiments, the thermal stress from the mismatched CTE is isolated from the temperature-dependent Young’s modulus. The measured results demonstrate convincingly that the SD-2-based device exhibits 36.73% lower CTE-induced thermal stress compared to the conventional BF33-based counterpart. The presented fabrication process can be used to fabricate a temperature-susceptible microelectromechanical systems sensor, such as an accelerometer and an inertia switch.