Revealing trap dynamics in p-GaN Gate HEMTs: a stretched exponential model for positive and negative bias-temperature instability

Abstract This letter proposes a stretched exponential model for positive and negative bias temperature instability (PBTI and NBTI) in p-GaN gate high electron mobility transistors (HEMTs). The model accurately captures the saturating behavior of threshold voltage shift ( Δ V TH ) during stress phase and is validated on three representative device architectures under varied stress and temperature conditions: a double-barrier cap layer p-GaN gate HEMT, a p–n junction gate HEMT, and a commercial EPC2033 Schottky-type p-GaN gate HEMT. By capturing both positive and negative Δ V TH under varying stress voltages and temperatures, the model reveals the roles of electron trapping, hole-assisted electron de-trapping, and hole trapping in governing threshold voltage instability. Elevated temperatures are shown to activate deeper traps and enhance carrier thermal energy enabling faster trap filling, while higher stress voltages also accelerate trap filling by providing cariers enough energy to overcome the potential barrier for being captured. This predictive framework offers a comprehensive and quantitative tool for assessing bias temperature instability in p-GaN gate HEMTs, supporting the reliable design of next-generation GaN-based transistors.