Design and optimization of embedded multi-field-plate structures for parasitic capacitance suppression in GaN-based MIS-HEMTs

Abstract This study investigates the performance and reliability optimization of GaN-based metal–insulator–semiconductor (MIS)-high electron mobility transistors (HEMTs) incorporating multiple field plates (FPs), with simultaneous suppression of parasitic capacitance. Based on experimental results, technology computer-aided design simulations are employed to gain a deeper insight into the influence of FP design variables. The multi-segment embedded source FP demonstrates several technical advantages, including the suppression of input capacitance ( C iss ) and reverse transfer capacitance ( C rss ), achieved by reducing the gate-to-source and gate-to-drain capacitances. The findings indicate that FP overlap, inter metal dielectric thickness, and FP electrode signals significantly affect device performance. Furthermore, the electric field distribution and the breakdown voltage are simulated and verified, which corresponds to the FP design comparison results. The structure reduces C iss by 46% and C rss by 98%, decreases the peak lateral electric field by 23%, and enhances the breakdown voltage to 1462 V, which demonstrates its suitability for high-frequency GaN-based MIS-HEMT applications. An optimized FP design strategy is proposed to suppress parasitic capacitance and reduce RC delay, contributing to enhanced dynamic performance and device reliability.