Hetero-dielectric step-shaped double-gate TFET on SELBOX substrate with SiGe pocket: suppressed ambipolarity, comprehensive DC, RF, and noise performance evaluation under thermal variation

Abstract In this manuscript, we present the design and simulation study of a novel tunnel field-effect transistor (TFET) design named hetero-dielectric step-shaped double gate TFET on selective buried oxide substrate (HD-SSDG–SELBOX TFET) to improve TFET performance and functionality over contemporary designs. This simulation study is performed in Sentaurus TCAD . The presented device introduces a stepped gate on a SELBOX substrate which helps improve the I ON / I OFF ratio while maintaining negligible ambipolarity when using a negative supply voltage at the drain. The structure employs an HD gate oxide and an overlapped gate pocket, which enhances the tunneling rate, thereby increasing the drain current. Additionally, the inclusion of a SiGe pocket introduced at the source side enhances the tunneling probability of charge carriers, further enhancing the ON-state current. The TFET design space is analyzed through parametric variation. An optimal structure is identified and supported with physical reasoning. Furthermore, analyzing the effect of temperature variation on the TFET is crucial to assess the device’s reliability under varying thermal conditions. The impact of temperature variation on DC parameters, including I DS –V GS behavior, subthreshold swing ( SS ) , I ON /I OFF ratio and radio frequency (RF) performance, across a broad temperature range of 300–450 K has been analyzed. The temperature dependency of a variety of RF metrics such as transconductance ( g m ), parasitic capacitances, cut-off frequency ( f T ), maximum oscillating frequency ( f max ), transconductance generation factor ( TGF ) , intrinsic delay, gain bandwidth product ( GBP ) , and transconductance frequency product ( TFP ) with temperature have also been studied. Moreover, the electrical noise characteristics of the HD-SSDG–SELBOX TFET are analyzed over 1 MHz–10 GHz. The suggested TFET structure demonstrates an impressive I ON /I OFF current ratio of 1.78×10 14 , with an I ON of 3.84×10 −4 A μ m −1 and an I OFF of 2.15×10 −18 A μ m −1 . It also exhibits a significantly lower SS of 16 mVdec −1 , suppressed I AMB conduction of 1.2×10 −17 A μ m −1 extending to a higher negative bias region, and enhanced transconductance (g m ) of 2.25×10 −4 S along with higher values of f T (1.58×10 11 Hz) and f max (2.42×10 12 Hz). A detailed evaluation of performance parameters provides valuable insights for device design. This implies that the suggested device exhibits improved reliability compared to standard TFETs in low-power operation under elevated temperatures.