Hot carrier degradation in p-MOSFETs at extremely low to room temperatures (77–370 K)

Abstract Conventional models of p-MOSFET hot carrier degradation (HCD) are based on interface trap generation and Arrhenius type temperature scaling. This study investigates p-MOSFET HCD across a wide temperature range (77–370 K) to ensure the reliability of peripheral CMOS in quantum-classical hybrid computing systems. Our key findings reveal a significant deviation from conventional models. Stress causes a positive threshold voltage shift (Δ V T > 0) at all temperatures because impact ionization generates electrons that are trapped in the gate oxide; the subthreshold slope changes little, indicating minimal interface trap creation. Crucially, at extremely low temperatures, suppressed phonon scattering the mean free path and allows carriers to retain higher kinetic energy before collision, favoring ‘lucky electron’ capture, leading to non-Arrhenius |Δ V T | scaling. A distinct anomaly at 77 K is the observation that the post-stress substrate current Δ I sub does not decrease after stress. Device lifetime estimated with an energy driven model significantly increases as temperature decreases. These results clarify the HCD mechanism at extremely low temperatures and offer physical insight that can support reliable CMOS operation from 77 to 370 K.