From atom to device multi-scale electro-thermal analysis of self-heating impacts in bulk vs SOI NSFETs for sub-3 nm technology node

Abstract As device scaling into the sub-3 nm technology node, self-heating effects have become a critical concern for the performance and reliability of gate-all-around nanosheet field-effect-transistors (NSFETs). However, conventional technology computer-aided design (TCAD) approaches often rely on bulk thermal parameters and neglect pronounced nanoscale effects, such as reduced channel thermal conductivity due to phonon-boundary scattering and significant interface thermal resistance, leading to inaccurate thermal predictions. We present a cross-scale electro-thermal simulation framework that combines atomic-level non-equilibrium molecular dynamics calculations with device-level TCAD, thereby incorporating size-dependent thermal conductivities and interface resistances into device analysis of bulk silicon and silicon-on-insulator (SOI) NSFETs. Under 3 nm node design rule of device geometry and bias ( V DS = V GS = 0.7 V ), the SOI device exhibits a peak channel lattice temperature of 348 K at the bottom nanosheet near the drain—approximately 11 K higher than its bulk counterpart, due to the buried oxide obstructing heat dissipation to the substrate. This exacerbated self-heating in SOI NSFET raises the thermal resistance by ∼33.7 % and induces a modest ∼1.96 % on-state current ( I ON ) degradation compared to the bulk device. Moreover, a parametric study of device geometry indicates that shorter channel lengths and greater nanosheet thicknesses can alleviate thermal hotspots while improving I ON , whereas the width can be flexibly adjusted to meet specific design requirements. Furthermore, the elevated lattice temperatures accelerate reliability degradation mechanisms (hot-carrier injection and bias-temperature instability), reducing the projected lifetime of the SOI device by factors of ∼1.92 and ∼2.68 relative to its bulk counterpart. These findings underscore the importance of electro-thermal co-design for ensuring performance and reliability in future nanoscale device technologies.