Reducing Josephson junction count in superconducting BNNs using a serial iterative accumulator

Abstract In this work, we propose a novel serial iterative accumulator (SIA) architecture for superconducting binarized neural networks (BNNs), which enables near-linear Josephson junction (JJ) scaling with bit width for the first time. This fundamentally overcomes the rapid JJ count explosion in conventional parallel multi-bit accumulation circuits. Based on the proposed SIA, we further develop an accumulation-based BNN (ABNN) architecture and systematically evaluate its resource efficiency and energy performance. Compared with the existing superconducting BNN architecture (JBNN), the proposed ABNN achieves a 97.7% reduction in JJ count and a 33% improvement in power efficiency, expressed as frames per second per watt (FPS/W). Moreover, by adopting energy-efficient rapid single flux quantum (ERSFQ) logic, the FPS/W metric can be further enhanced by up to 17× relative to the original JBNN design. These results clearly demonstrate that the proposed ABNN provides a compact, scalable, and energy-efficient architecture for large-scale superconducting neural network systems.