Thermal-aware performance analysis of a junctionless T-shaped nanosheet FET: a comprehensive study on digital, analog, RF, and circuit applications

Abstract For the first time, thermal investigation is carried out for the Junctionless (JL) T-shaped (T) Nanosheet (NS) FET at the sub-5 nm technology node. Using a well-calibrated TCAD setup, comprehensive insights into digital, analog, RF, and circuit applications are obtained by varying the temperature (T) from 250 K to 400 K. A significant digital improvement is observed as T decreases, showing an ∼7-order reduction in I OFF (from ∼10 –13 to ∼10 –20 ) with an enhanced I ON /I OFF ratio of ∼10 12 . The SS and DIBL show ∼41.3% and ∼87.25% reduction, respectively, when T is lowered from 400 K to 250 K, ensuring reliable operation for space electronics operating under extreme thermal cycling. The intrinsic gain (A V ) improves by ∼26% at 250 K compared to 400 K, indicating higher amplification efficiency and better signal integrity for low-temperature and low-power analog design. The cutoff frequency (f T ) increases by ∼56% at lower temperatures, demonstrating suitability for high-speed, low-temperature RF applications. Common Source (CS) amplifier analysis shows ∼60 mV output for a 10 mV input at 250 K, giving a gain of ∼6, which is ∼40% higher than at 400 K. These enhancements establish the JL-T-NSFET as a strong candidate for cryogenic low-power analog IC applications.