An energy-efficient 11T SRAM cell architecture with write-assist mechanism at sub threshold voltage for biomedical applications

Abstract The proposed 11T (P11T) cell is constructed using the 32 nm technology node at a low voltage of 500 mV. The read and hold operations had static noise margins (SNMs) of 184 mV and 197.26 mV, respectively, but the write operation displayed SNMs of 265 mV. The write and read access times of the cell were determined to be 16.24 ps and 11.38 ps, respectively. Additionally, the performance under 3 σ global variance was evaluated using Monte Carlo analysis with a sample size of 5000. The P11T bit cell’s low power consumption during all operations was another notable feature. For a sample size of 5000, Monte Carlo simulations showed stability improvements during read and hold procedures. Additionally, dynamic power consumption for read and write operations of the cell was minimal compared to other SRAM cells. All simulations and analyses were conducted using LT-spice software. The bit cell occupies an area of 3.228 μm2. Comparatively, read power for the pre—existing 7T1,7T2, 9T1, 9T2, 10T1, 10T2, 11T1, 11T2 and 11T3 cells is 24.3 μW, 27.6 μW, 28.2 μW, 27.4 μW, 34.6 μW, 29.64 μW, 14.2 μW, 16.8 μW, and 26.9 μW respectively, and write power for the pre—existing 7T1,7T2, 9T1, 9T2, 10T1, 10T2, 11T1, 11T2, and 11T3 cells is 2.6 μW, 5.4 μW, 4.2 μW, 5.2 μW, 6.4 μW, 7.2 μW, 4.1 μW, 6.2 μW, and 7.4 μW respectively and the read and write power of the proposed 11 T cell is found to be 18.26 μW and 5.32 μW, respectively.