Suppressed channel rectangular core-shell DG-JLFET for improved DC and analog performance

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Authors: Atul Himral, Rajneesh Sharma, Mohit Agarwal
Cited by: 0
References: 25

Abstract

Abstract This paper presents a comprehensive analysis of the DC and analog performance of the Suppressed Channel Rectangular core–shell Double Gate Junctionless Field Effect Transistor (SC_RCS_DGJLFET). The study focuses on optimizing core–shell thickness, gate dielectric materials, and channel length to enhance device performance. The core thickness is varied between 2 nm and 5 nm, while the shell thickness is varied between 2 nm and 6 nm. The results show that a 3 nm shell and 2 nm core achieve the highest I ON /I OFF ratio of 8.24 × 10 12 and the lowest OFF-state current (I OFF ) of 2.65 × 10 −17 A. The ultra-low I OFF is attributed to channel suppression and an intrinsic core, ensuring complete volume depletion in the subthreshold region. The impact of gate dielectrics was also examined by comparing high-k materials (HfO 2 , Si 3 N 4 ) with SiO 2 . The proposed device with SiO 2 demonstrated the lowest I OFF (2.65 × 10 −17 A), DIBL (18 mV V −1 ), and subthreshold slope (61.83 mV decade−1), eliminating the stringent need for high-k dielectrics. The study investigates channel lengths from 5 nm to 30 nm, encompassing both low and high technology nodes. The optimized SC_RCS_DGJLFET exhibits a low leakage current of I OFF = 10 −13 and I ON ​/I OFF ​ ratio of 8.24 × 10 9 . Even at an aggressively scaled channel length of 5 nm, the device maintains excellent performance, although both the subthreshold slope (SS) and drain-induced barrier lowering (DIBL) values increase slightly due to short-channel effects. The analog performance of the proposed SC_RCS_DGJLFET was evaluated through parameters such as transconductance (g m ), output conductance (g d ), intrinsic gain (A V ), and Early voltage (V ea ) across varying core–shell thicknesses. The device achieved a peak gm of 1600 μS μm −1 and an Early voltage of 19 V, surpassing reported double-gate JLFET designs. These improvements, driven by optimized core–shell thickness, highlight the SC_RCS_DGJLFET as a highly efficient structure for next-generation analog and mixed-signal applications.

Fields of Study & Subjects

Advancements in Semiconductor Devices and Circuit Design Semiconductor materials and devices 2D Materials and Applications

Publication details

Journal / source
Physica Scripta
Volume
101
Issue
9
Pages
095902–095902
Publication date
16 February 2026
Language
EN