Hardware-efficient quantum arithmetic logic units for square lattice architectures

Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.