Hardware-accelerated GNN-based hit filtering for the Belle II Level-1 trigger

Abstract We present a hardware-accelerated hit filtering system employing Graph Neural Networks (GNNs) on Field-Programmable Gate Arrays (FPGAs) for the Belle II Level-1 Trigger. The existing track trigger exhibits reduced efficiency, in particular for short and endcap region tracks, due to its requirement of aligned hits in the majority of detector layers. An efficient hit filter enables the subsequent track trigger to operate with relaxed requirements, allowing higher track finding efficiency without increasing the Level-1 trigger rate. The proposed GNN system exploits spatial and temporal correlations among sense wire hits for detector-level background suppression. The network is optimized for high-throughput hardware operation via quantization, pruning, and static graph-building. Sector-wise spatial parallelization permits scaling to full-detector coverage while satisfying Belle II latency and throughput requirements. At 32 MHz throughput and sub-microsecond latency, the system achieves an offline-validated 83% background hit rejection at 95% signal hit efficiency. This work demonstrates scalable, low-latency GNN-based hit filtering on FPGA for real-time data reduction in high-luminosity collider environments.