A calibratable low-power SAR ADC for VLAST silicon microstrip detector

Abstract This paper presents a 12-bit, 2 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) developed as a dedicated on-chip digitization module intended for integration with a front-end readout ASIC previously designed by our group for the silicon-strip detector of the Very Large Area Gamma-ray Space Telescope (VLAST). The proposed ADC is designed to address the integration and power challenges of the large-scale detector system, which consists of approximately 1.38 million channels. In this work, the ADC was fabricated and tested as an independent prototype chip using a 180 nm CMOS process. The purpose of this prototype was to verify the circuit functionality and performance prior to system-level integration. The design employs a V cm -based capacitor-switching method to reduce dynamic power consumption and implements an LMS-based background calibration algorithm to enhance linearity. Measurement results indicate that the prototype operates at 2 MS/s with a power consumption of 1.8 mW, achieving 12-bit resolution. After calibration, the measured ENOB is 10.14.