Design and first results of COFFEE3: a 55 nm HVCMOS pixel sensor prototype for high-energy physics applications

Abstract Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed using a 55 nm High-Voltage CMOS (HVCMOS) process. The primary objective is to achieve a time resolution of a few nanoseconds under a hit density of up to 100 MHz/cm 2 , while maintaining fine spatial resolution (∼10 μm) and reasonable power consumption (< 200 mW/cm 2 ). Building on the process validation of the COFFEE2 prototype, this work presents the design and preliminary test results of COFFEE3 — a prototype integrating two distinct readout architectures. Architecture 1, tailored for the current triple-well process, adopts NMOS-only in-pixel circuitry and innovative column-level readout to handle high hit densities. The time walk of pixel-level signal is controlled within 10 ns, and the Time of Arrival (TOA) and Time over Threshold (TOT) are measured with a system clock with the period of 25 ns in peripheral circuits. Architecture 2, developed for future possible processes with p-type buried layer isolation, features pixel-level time measurement and storage. A chip-level Time-to-Digital Converter (TDC) is used and the part of Voltage-Controlled Delay Line (VCDL) is copied in each pixel to get a high time resolution. The TOA resolution is estimated to be 4.2 ns and the TOT resolution 8.4 ns. COFFEE3, with a layout size of 3×4 mm 2 , was manufactured and has undergone preliminary tests. Charge injection tests for analog circuits, and laser tests for full readout chains, confirm that both architectures operate as expected. Next step work will focus on characterizing key performance such as the timing resolution, radiation hardness, and tracking performance of minimum ionising particles.