Optimization of GaN device gate drive circuit based on EZDrive architecture and suppression of voltage ringing

Abstract Gallium nitride (GaN) power devices often exhibit output voltage ringing during high-frequency switching due to parasitic parameters. Traditional forward-biased drive schemes not only struggle to effectively suppress this issue but also carry a high risk of false turn-on. Therefore, this study proposes three optimization measures based on the EZDrive architecture: (1) Optimizing passive RC network parameters to reliably generate a negative turn-off voltage at MHz-level frequencies; (2) Matching gate resistors with ferrite beads to synergistically suppress resonance; (3) Addressing variations in gate voltage tolerance across different GaN devices and compatibility with existing controllers by employing a diode clamping network to achieve adjustable clamping threshold gate voltage protection and level adaptation. To validate this approach, an LTspice simulation model was established based on the measured characteristics and datasheet parameters of the Infineon GS61008P enhancement-mode GaN HEMT, and tested at a frequency of 1 MHz. Results demonstrate that compared to traditional approaches, the proposed design actively generates a turn-off negative voltage, effectively suppressing false turn-on. It stably regulates V gs within the −5 V to +7 V range, aligning with the device’s safe operating area of −10 V to +7 V. Voltage ringing duration decreased from >180 ns to