A lightweight frequency interleaving DAC architecture: design and validation

Abstract Frequency interleaving DAC (FI-DAC) holds great prospect in overcoming the bandwidth limitation of the DAC. Although this technology increases the output bandwidth, it also introduces challenges related to the increased system complexity and resource overhead. Research indicates that current FI-DAC system requires multiple digital signal processing (DSP) tasks for system construction and error correction, leading to increased hardware resource consumption, making it suitable primarily for offline, non-real-time applications. To address this issue, a lightweight structure is proposed based on spectral characteristics. It removes one type of component each in the digital and analog domains from the original architecture while maintaining the same output performance, which simplifies the signal processing chain. Through simulation and experimental validation, the effectiveness and feasibility of the novel architecture are demonstrated. Specifically, experimental results with a two-channel implementation demonstrate that the proposed architecture doubles the output bandwidth while reducing LUT usage by 56.6% and DSP slices by 35.3% compared to conventional architecture. Furthermore, the system maintains a Spurious-Free Dynamic Range (SFDR) of 41.22 dBc, confirming that efficiency gains are achieved without compromising signal quality.