Nanocopper-based low-temperature interconnection technology: advances in material systems, sintering mechanisms and packaging applications

Purpose This paper aims to systematically summarize recent advances in low-temperature interconnection using Cu nanoparticles, nanoporous Cu and one-dimensional (1D) nanocopper arrays, clarify their advantages and bottlenecks and provide theoretical support and technical references for industrial applications to sectors including new energy vehicles and 5G/6G communications. Design/methodology/approach This study reviews synthesis, anti-oxidation and sintering mechanisms of Cu nanoparticles, nanoporous Cu and 1D arrays for low-temperature interconnection. It analyzes how sintering parameters (temperature, pressure, time, atmosphere) impact joint reliability (mechanical, electrical, thermal). By evaluating and comparing these three systems based on current research, this work provides a comprehensive framework for understanding interfacial behaviors and performance in advanced packaging. Findings Nanocopper materials (nanoparticles, nanoporous Cu and 1D arrays) enable high-performance, low-temperature sintering for robust interconnections with excellent conductivity and heat resistance. While nanoparticles offer high strength, they face oxidation and densification issues. Nanoporous Cu provides superior bonding efficiency without organic residues, and 1D arrays offer directional conductivity for complex packaging. Ultimately, optimizing sintering parameters is essential to regulating microstructure and ensuring the mechanical, electrical and thermal reliability of the resulting joints. Originality/value This review summarizes nanocopper-based low-temperature interconnection progress, compares Cu nanoparticles, nanoporous Cu and 1D nanocopper arrays and highlights their respective advantages and bottlenecks. By clarifying the mechanisms of sintering parameters and outlining future research directions – focusing on stability, compatibility and reliability – this work provides a framework for addressing the packaging challenges of high-power devices.