Pushing the Limits of PIN Photodiode Direct Detection: Integrate-and-Dump Receivers With CDS Equalization Closing the Gap to the Quantum Limit to 13.9 dB

This paper presents a highly sensitive monolithic direct detection receiver with dot-cathode PIN photodiode, integrate-and-dump front-end, and correlated double sampling (CDS) equalization. Compared to previous work, we significantly improve front-end sensitivity by numerical optimization. Three different common-source and inverter front-ends, based on standard and low threshold voltage (LVT) transistors, are realized in 180 nm high-voltage CMOS. Sensitivity measurements show an advantage of around 1 dB for the common-source front-end over the inverter front-end. The sensitivity improvement of LVT transistors over standard transistors is around 2 dB. The receiver with LVT common-source front-end achieved the best sensitivity of −53.1dBm (−48.0dBm) at 100 Mbit/s (200 Mbit/s), BER = 10−6, λ = 642nm, and 50% return-to-zero (RZ) on-off keying (OOK) modulation. That equals a gap to the shot noise quantum limit (QL) of 13.9 dB (15.9 dB). Moreover, we verify our previous post-processing CDS method through an experimental comparison to on-chip CDS.