SAPHO—Scalable-Architecture Processor for Hardware Optimization: An FPGA Customizable Implementation Approach

Soft-core processors are increasingly being used in Field Programmable Gate Arrays (FPGAs) to implement complex functions at critical points in embedded systems, where a pure firmware solution would demand excessive development effort or hardware resources. However, most existing processors rely on a fixed architecture, allocating the same amount of logic resources regardless of the application. This typically results in hardware over-provisioning, oversized data word lengths, and unnecessary power consumption. To overcome these limitations, this work presents SAPHO, a self-scalable processor that automatically adjusts its program and data memories as well as its arithmetic and logic circuits according to the software requirements. This design paradigm reduces hardware waste, lowers logic element utilization, and enables more energy-efficient execution compared to conventional soft-core processors. In addition, SAPHO incorporates a combinational Arithmetic Logic Unit (ALU), configurable for fixed or floating-point operations, that guarantees the execution of one instruction per clock cycle without pipeline stalls. Performance evaluation demonstrates that, when compared to a widely adopted commercial soft-core processor (NIOS II), SAPHO achieves lower hardware cost and execution time while maintaining scalability and flexibility for different embedded applications. Experimental results show that SAPHO executes all arithmetic operations in a fixed sequence of 13 clock cycles, whereas equivalent operations on the NIOS II require from tens to thousands of cycles depending on the processor configuration and data type. In an 8-point FFT benchmark, SAPHO reduces execution time by 77.36% compared to the fastest NIOS II configuration. Furthermore, SAPHO requires fewer logic elements (LEs) and exhibits lower dynamic core power consumption, showing a reduction in dynamic core power consumption ranging from 15% to 33% compared with the NIOS II variants. These results demonstrate that SAPHO achieves lower hardware cost and faster execution while maintaining scalability and flexibility for different embedded applications.