An Area-Efficient Wideband CMOS SPDT Switch for High-Frequency Applications

This work presents a wideband, low-power single-pole double-throw (SPDT) switch implemented in a 65-nm RFCMOS process. A π-type matching network is introduced at the common port (PTR) to simultaneously improve insertion loss and isolation, extending the operating range from approximately 20 GHz to 60 GHz. To suppress core-area growth, transistors are placed inside the inductor, and the layout is arranged to minimize magnetic coupling between the inductor and the transistors so that high-frequency operation remains stable. Measurements show insertion loss ≤ 2.3 dB, return loss ≥ 12 dB, and isolation ≥ 26.8 dB over DC-40 GHz. The input 1-dB compression point is about 9-10 dBm, indicating suitability for medium-power applications. These results indicate an SPDT switch that achieves wide bandwidth, low loss, high isolation, and area efficiency.