Ultra-Fast and Accurate Estimation of Large-Scale and Multi-Level Mesh-Based On-Chip Architectures Using Machine Learning and Multiprocessing

Packet Switching On-Chip Network technology has taken over conventional bus-based on-chips since it combines multiple cores into a single chip, enabling the implementation of numerous complicated applications. The evaluation of NoC design performance depends mainly on simulation, which becomes very slow with increasing architectural size and needs more information about how different design parameters affect the actual performance of the network. As a result, using simulation for optimization is exceedingly challenging, and these systems must be verified using distinct simulated traffic flows of various topological sizes. Thus, we present a Machine Learning (ML) framework to examine the design parameters of 2D and 3D NoC architectures paired with multiprocessing since these need to be evaluated on different configurations. The Multiprocessing Regression Framework (MRF) is the name of this framework. By utilizing different machine learning regression models, this approach forecasts NoC parameters while considering a range of various simulated traffic flows. The proposed approach can be tested on 2D and 3D NoC designs and may be used to analyze performance, area, and power architectures. The outcomes were compared with those produced by the popular cycle-accurate Booksim NoC simulator. Topology sizes ranging from 2×2 to 50×50 were tested alongside varying injection rates, virtual channels, and various network traffic behaviors. The proposed design put forward achieved a speedup between 1000× and 1500×, while the prediction error was approximately 8% to 10%.