Suppressing the Capacitive Coupling by Adjusting the Precharge Biasing Scheme in a Two-Transistor Dynamic Random-Access Memory Operation

In this study, the impact of capacitive coupling (CC) caused by the parasitic capacitance components of metal-oxide semiconductor field effect transistors (MOSFETs) on the data stored in a two-transistor dynamic random-access memory (2T DRAM), is investigated, and a method to suppress CC is proposed. Recently, processing-in-memory (PIM) has been getting increasing popularity as one of the emerging technologies for future computing with a focus on data-centric operations due to increasing applications which deal with large amounts of data. 2T DRAM has advantages at high-speed inference operations, cell scalability with truncation of the bulky capacitor, and full Si processing-capability, which makes the 2T DRAM PIM more favorable in chip implementation. However, the 2T DRAM cell has a weakness in that it is highly susceptible to coupling, because the storage node (SN), where data is stored, exists between the two transistors at floating state. This work investigates the cause of the CC and explains how to the precharge voltage is used to reduce the effect of CC in 2T DRAM. Furthermore, the disturbance based on the data stored in each cell of a 32 × 32 array is analyzed to determine its impact on read operations. The overall circuit simulations are based on the 65-nm standard process and the effects of parameters in its model library are examined.