Interleaver Design for Parallel Concatenated Block Codes With Arbitrary Lengths

Parallel Concatenated Block (PCB) codes are conventionally constituted by two identical linear systematic block codes, as component codes, linked by an interleaver. In general, the interleaver length of the PCB code (or message length) is the square of the message length of the constituent codes. This feature enables the interleaver to distribute bits from a message block across various interleaved blocks. Such a permutation process is not achievable from a PCB code whose interleaver length is shorter than the square of the message length of its component codes. As more than one bit of a message block is placed at an interleaved block, the minimum weight of the PCB code can be obtained from messages with weight greater than one. Such a structure will consequently deteriorate the PCB code's error-correcting performance. To overcome this problem, the paper presents a new scheme of interleavers for PCB codes, whose lengths are multiples but not squares of the message length of PCB's component codes. A permutation algorithm is implemented based on the low-weight distribution of component codes to ensure that the PCB code has an outstanding error-correcting capability. Indeed, the interleaver rearranges message bits such that the minimum weight of the PCB code is obtained from messages with weight one. The analysis and simulation results confirmed that the newly proposed interleaver outperforms the conventional interleavers for PCB codes. The improvement is achieved at medium to high signal-to-noise ratios, where the code's error floor is encountered. It is also concluded that PCB codes constructed using the proposed interleaver outperform the well-known Cyclic Redundancy Check (CRC)-polar codes used in global standards. This is evident for long-length-based codes.