Analytical Extraction of Thermal Resistance in Power Semiconductors Using Structural Function Derivatives and Series Resistance Modeling

Junction-to-case thermal resistance (RthJC) is a critical parameter for assessing the reliability and thermal performance of power semiconductor devices. Conventional JEDEC-based extraction relies on detecting the divergence of thermal capacitance curves measured with and without grease, but this criterion is highly sensitive to interface variability and capacitance-delta noise, often leading to inconsistent or overestimated RthJCvalues. To address these limitations, we present an analytical extraction method that applies derivative and curvature analyses to the structural function, enabling clear identification of thermal boundaries and quantitative separation of chip-, die attach-, and lead frame-level thermal resistances. A series-resistance model is used to validate internal consistency by reconstructing the total RthJCfrom the extracted layer components. Experiments on silicon (Si) and silicon carbide (SiC) power devices confirm the method’s reproducibility and reveal material-dependent thermal behavior. In particular, the SiC chip exhibits intrinsically lower thermal resistance than Si, while the dominant contribution to total RthJCoriginates from the lead-frame region—indicating that package-level optimization, rather than chip-level modification, offers the most effective path to reducing overall thermal resistance. The proposed method provides a grease-insensitive and analytically defined, physically grounded framework for thermal characterization, offering improved robustness and internal consistency, and design insight for next-generation power semiconductor packages.