A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit complexity. The proposed architecture employs a constant-slope capacitor digital-to-analog converter (CDAC) based digital-to-time converter (DTC) to narrow the effective range of the time-to-digital converter (TDC), thereby enabling high-resolution phase detection without requiring a wide dynamic range. A feedforward spur cancellation filter suppresses residual fractional errors caused by DTC gain error and nonlinearity. In addition, an asynchronous duty-modulation unit (DMU) dithers the LSB of digitally controlled oscillator (DCO) to reduce DCO quantization noise, distribute it across finer time segments and lower the integrated RMS jitter. Fabricated in a 65-nm CMOS process, the prototype ADPLL consumes 6.92 mW in steady-state operation, achieving 0.73 ps integrated RMS jitter and –71.6 dBc worst-case fractional spur. The results demonstrate the effectiveness of combining snapshot-based phase detection, feedforward spur cancellation, and asynchronous pulse-width dithering of DCO.