Impact of MAC Unit Design Architectures and Their Applications in Modern Computing: An In-Depth Review

A fundamental computational block essential for computing devices is the multiplier-accumulator (MAC) unit. A MAC unit repeatedly performs a multiply and add operation commonly used in many data processing and artificial intelligence (AI) applications. This article comprehensively analyzes MAC unit architectures, focusing on high-throughput configurations such as systolic arrays and tree-based multipliers integrated into AI, high-performance computing (HPC), and digital signal processing (DSP) hardware. It traces their evolution from serial and pipelined designs to specialized precision formats (fixed and floating point) used in modern workloads. We explore modern design concepts, including approximate MACs utilizing truncated arithmetic, sparsity-aware designs that bypass zero-value operands, and units optimized for binary neural networks. The article also examines the transformative impact of In-Memory Computing (IMC) MACs, which leverage crossbar arrays to mitigate data movement bottlenecks. Furthermore, we contextualize these advancements within leading hardware accelerators, such as Google Tensor Processing Unit (TPUs), field programmable gate arrays (FPGAs), and NVIDIA Tensor cores. We identify persistent challenges, including power constraints and reliability in nanoscale technologies, and also outline future trends such as photonic MACs and adaptive bit-width scaling, which can serve as a guide for future innovation in this vital field.