The DiQuNET Architecture for the Control of Quantum Processors: The Case Study of Trapped Ions

[Background] Scalability is the only DiVincenzo criterion that has not yet been achieved at utility-scale and fault-tolerant levels by any quantum processor. These quantum machines are governed by a classical control system that must scale along with the quantum objects it controls. For the case study of trapped-ion quantum processors, mostly massive room-temperature, rack-based, and non-integrated solutions for its control system are described in literature, which is neither scalable nor efficient. Thus, the control system poses an engineering bottleneck for the scalability of quantum processors. [Objective] Therefore, this study aims to address this gap by proposing a scalable microelectronics-based control architecture blueprint. [Methods] Our method relies on an electronic system-level top-down design methodology, and we illustrate the concepts through a case study. [Results] In this study, we first challenge thestatus quofor the use case of a quantum processor and propose a more pragmatic approach. Second, we present the DiQuNET architecture, which is a system-level architecture for the control of a quantum processor. Finally, we present a case study in which we map the architecture to control a specific quantum processor technology, subsystem, and functionality. [Conclusion] Our proposal is an innately scalable and controldistributed system architecture whose features aim to support the execution of a quantum algorithm at utility-scale levels and embed hardware to support fault-tolerance. It raises the hardware interface of the processor to an algorithm level and opens the door to the joint community and industrial realization of the control system for quantum processors.