An Efficient High-Throughput FFT Architecture to Process Twin Real-Valued Data-Streams With Normal I/O Order

This paper proposes an efficient pipelined modified MDC-based (Multipath Delay Commutator) radix-2 Real-valued Fast Fourier Transform (RFFT) architecture with high throughput. The RFFT is an optimised Fast Fourier Transform (FFT) architecture to process real-valued signals. Though several RFFT architectures are available, they have low throughput and lack a better reordering methodology. Many prior designs process one sample per clock cycle and require relatively more hardware, and data reordering is required at the input and output. The proposed architecture is designed based on an overlapped data flow graph of two independent RFFTs, which can process two real-valued data streams simultaneously. It takes two real-valued samples per data stream per cycle in normal order, and generates output in normal order with the help of a novel reordering circuit. The computational complexity of the proposed design is significantly lower than the prior designs. The adder and register complexity of the proposed design is 50% less than the earlier works, and the proposed design delivers better throughput as well.