An Efficient Racetrack Cache Architecture for Performance-Area-Energy Co-Optimization

Prior RTM cache architectures, originally designed for smaller caches, become suboptimal when scaled to larger RTM Last-Level caches (LLCs), because they prioritize performance over energy and area efficiency. These architectures typically employ wide interconnects equal to the cache line size, leading to significant energy and area overheads. To address these limitations, we propose a narrow-width data array layout combined with a hybrid tag-store design, enabling an RTM-based LLC that achieves substantial energy and area improvements while maintaining performance comparable to wide-interconnect designs. Furthermore, we introduce organizational and data layout modifications that facilitate the use of narrower interconnects in high-capacity RTM LLCs. To mitigate the performance penalty of our fine-grained RTM LLC organizations, we propose architectural enhancements to the RTM controller and datapath that improve access parallelism. Overall, this fine-grained RTM cache architecture is optimized for energy (33.6% saving) and area (20.5% less area) efficiency with only 2.5% performance degradation compared to state-of-the-art.