High-Performance and Energy-Efficient Computing-In-CAM Design for Binary Neural Network Acceleration

The importance of convolutional neural networks (CNNs) is increasing in various domains, including image processing and natural language processing. While powerful processors enable efficient training and validation, achieving high-throughput inference on resource-constrained embedded systems remains challenging. Binary neural networks (BNNs) simplify computation by reducing model complexity and can be efficiently implemented using content-addressable memory (CAM), which replaces convolution computation with search operations. However, prior CAM-based BNN accelerator (BNN-CAM) requires many cycles for input reordering leading to performance and energy degradation. To overcome this drawback, we propose a novel BNN-CAM that integrates a multi-bitline structure and a single-cycle reordering technique, reducing reordering cycles by sixfold while improving energy efficiency through an overwrite termination feature. The proposed design is implemented on the second convolutional layer of the LeNet-5 model using 28-nm CMOS technology. The results show a 53.4% latency improvement and a 16.2% gain in energy efficiency compared with conventional BNN-CAM, leading to a 41.0% enhancement in the figure of merit and an overall power efficiency of 417.0 TOps/W.