Leveraging Transformer Networks for Enhanced Detection of Hardware Trojans via Power Side-Channel Analysis

The proliferation of Hardware Trojans (HTs) poses a critical threat to the reliability and security of integrated circuits (ICs), particularly in safety and mission-critical domains. Conventional detection approaches either rely on destructive imaging or trusted golden chips, both of which are costly and limited in scalability. This study introduces a golden-chip-free, non-destructive framework for Hardware Trojan Detection (HTD) based on transformer architecture applied to Power Side-Channel (PSC) signals. The research contribution presents the first systematic performance comparison between decoder-only (GPT-like) and encoder-only (BERT-like) models, as well as full encoder–decoder transformer models, for time-series PSC analysis. To adapt these models to the hardware security domain, side-channel traces are normalized, reduced via principal component analysis, and embedded with positional encodings to preserve temporal structure. The framework is evaluated on the publicly available Trojan Power & EM Side-Channel dataset using 10-fold cross-validation. Results show that GPT-based and BERT-based models achieve 66.32% and 79.41% accuracy, respectively. While the full transformer network significantly outperforms them with 92.43% accuracy, 92.44% precision, 92.43% recall, and an F1-score of 92.31%. These findings demonstrate the potential of attention-based architectures to capture subtle variations in PSC signals without requiring a golden reference chip. The study contributes a reproducible and comparative benchmark for transformer-based HTD, offering a scalable pathway toward more robust and interpretable hardware security solutions.