A 6-Gsps/Lane MIPI C-PHY Receiver With Glitch Noise-Free Clock Recovery Circuit

A mobile industry processor interface (MIPI) C-PHY receiver is proposed that includes a clock recovery circuit to eliminate glitch noise generated during the process of recovering the clock through edge-combining three signals with three voltage levels received from the MIPI C-PHY. The proposed clock recovery circuit removes glitch noise from the recovered clock by adaptively controlling the delay of the pulse generator based on the results of sampling even and odd data on both edges of the recovered clock. The proposed MIPI C-PHY receiver is implemented in a 65 nm CMOS process with a 1.2 V supply voltage and occupies an active area of 0.105 mm². It supports 6 Gsps per lane, recovers a 3 GHz clock, and outputs even and odd data at 3 Gsps using the recovered clock. The measured peak-to-peak time jitter and RMS time jitter of the recovered 3 GHz clock are 20 ps and 2.4 ps, respectively. The 6 Gsps MIPI C-PHY receiver supports an effective bandwidth of 13.68 Gbps, achieving an energy efficiency of 1.64 pJ/bit.