Balancing Accuracy and Resources in FPGA Approximate HLS: Model-Free Versus Model-Based Approaches

Approximate Computing (AxC) enhances energy and resource efficiency by intentionally relaxing accuracy requirements, offering an attractive trade-off for FPGA-based hardware accelerators. In Approximate High-Level Synthesis (AHLS), effective Design Space Exploration (DSE) is crucial for identifying Pareto-optimal solutions that balance accuracy and hardware cost. However, existing DSE approaches rely on either model-based analytical estimations or model-free evaluations, each presenting trade-offs in speed, fidelity, and scalability. This work introduces and compares two complementary DSE strategies for AHLS: (i) a DFG-based approach that analytically estimates error propagation, and (ii) an Input-Aware Heuristic (IAH) that evaluates candidate approximations using the actual application behavior. Both approaches leverage a pre-characterized library of approximate arithmetic components and perform post-HLS evaluation to assess FPGA resource utilization and accuracy. Experimental results across image processing applications demonstrate that the IAH identifies broader and more accurate Pareto fronts, achieving up to 11 percentage points higher savings in LUT and FF usage compared to static DFG-based exploration while maintaining accuracy within defined thresholds. These findings show that model-free guidance significantly improves AHLS exploration.