Ψ -xLSTM: Automated Behavioral Verilog-A Generation From Distilled Physics-Informed xLSTM Networks for High-Frequency Device Modeling

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Authors: Sorin Liviu Jurj
Cited by: 2
References: 20

Abstract

Physics-Informed Neural Networks (PINNs) have emerged as a powerful tool for device modeling, yet they suffer from a fundamental spectral bias, often failing to capture high-frequency transient dynamics essential for modern circuit simulation. While recent implementations of Extended Long Short-Term Memory (xLSTM) networks have successfully mitigated this bias by leveraging exponential gating and matrix memories, they introduce prohibitive computational complexityO(N2)that renders them unsuitable for standard compact modeling and hardware deployment. In this work, we introduce Ψ-xLSTM, a framework that extends the Ψ-HDL methodology to recurrent architectures, enabling the automatic generation of efficient behavioral Verilog-A models that retain the high-frequency fidelity of xLSTMs. We propose a novel Recurrent Relation-Aware Distillation (RRAD) strategy that preserves temporal dynamics and targets the specific architectural innovations of xLSTM. First, we demonstrate that the xLSTM exponential gating mechanisms can be clustered to reveal discrete, physically interpretable time constants (relaxation times), replacing continuous gate values with sparse, physics-based parameters. Second, we apply structural compression to the xLSTM matrix memory (mLSTM), proving that the governing physics of device dynamics resides in a low-rank subspace, allowing the dense matrix to be collapsed into a few dominant eigen-modes. We validate Ψ-xLSTM on high-frequency transient memristor dynamics, where the framework achieves the spectral accuracy of full xLSTM-PINNs while reducing parameter count by up to 84%. Extended evaluation across additional spectral-bias baselines, multiple device classes, small-signal and large-signal active-device benchmarks, and publicly available experimental datasets further demonstrates the robustness and broader applicability of the approach. SPICE circuit simulation validates the complete model generation pipeline with a mean absolute error of 0.40 mA, confirming quantitative accuracy. The resulting models are automatically exported as compact behavioral Verilog-A code that captures high-frequency harmonics missed by standard PINNs, while simulating 7.6× faster in Python, with substantial additional gains expected in compiled SPICE due to elimination of matrix-memory overhead, supported by complexity analysis and behavioral simulation validation.

Fields of Study & Subjects

Model Reduction and Neural Networks Tensor decomposition and applications Low-power high-performance VLSI design

Publication details

Journal / source
IEEE Access
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
14
Pages
52272–52289
Publication date
1 January 2026
Language
EN