Measurement-Based Parasitic Inductance Network Identification for Multichip Power Modules Based on Inductance Matrix of Loop Wiring Paths

Internal parasitic inductance is a critical factor in fast-switching silicon carbide (SiC) power modules, making its accurate extraction essential for reliable design. Although measurement-based extraction methods are highly desirable for quality assurance, their practical difficulty has led to the widespread use of simulation-based partial element equivalent circuit (PEEC) methods. The PEEC method evaluates a branch-based inductance matrix, enabling detailed extraction that fully accounts for the magnetic coupling of each branch. However, applying the PEEC method in experimental setups is challenging because directly measuring the extremely small self-inductances of each branch makes the results highly susceptible to the parasitic inductance of measurement cables and requires a large number of measurements. To overcome these limitations, this study proposes extracting the parasitic inductance network by measuring the inductance matrix of closed loops formed by internal wiring paths, rather than the conventional branch-based matrix. Because these closed loops provide a closed current path, capacitors can be inserted to induce parallel resonance with the parasitic inductances, enabling extremely small inductances to be accurately measured as high impedances. Furthermore, this approach reduces the number of required measurements, while still accounting for magnetic couplings similar to the PEEC method. The validity and accuracy of the proposed methodology are demonstrated through experimental verification using a prototype SiC power module.