Efficient Approximate Recursive Multipliers (EARM) for Area and Power Optimized Image Processing Applications

This paper proposes a novel approximate multiplier designed to improve efficiency in digital systems by exploiting controlled approximation while minimizing hardware requirements. Four incremental gate-level variants architectures of approximate multipliers are developed and used as building blocks to construct scalable 8 × 8 and 16 × 16 configurations. The proposed multipliers are synthesized using the Cadence Genus tool to validate their effectiveness. A comprehensive comparative analysis is performed against state-of-the-art designs in terms of area, power, and delay. Notably, the proposed 8×8 approximate multiplier (S8-4) achieves up to 73.09% reduction in area, 74.54% reduction in power consumption, and 20.98% reduction in delay compared to an exact multiplier, while maintaining competitive accuracy. Furthermore, the proposed designs demonstrate superior power efficiency compared to existing approximate multipliers. The effectiveness of the proposed multipliers is validated through image smoothing, sharpening, and image multiplication applications, highlighting their suitability for error-resilient image processing systems.