Ultralow-Voltage NMOS-Only Voltage Reference With High-Frequency PSR Optimization via Decoupling Pseudo-Resistor

Operating integrated circuits at minimal supply voltage and power levels has become a crucial challenge to support the development of energy-harvested smart sensing devices. In this work, building upon a single-branch 3-transistor voltage reference (VR) presented in a previous publication, we propose a novel NMOS-only 4-transistor VR, combining a self-cascode technique with high-frequency power-supply rejection (PSR) optimization by means of a strategically placed decoupling pseudo-resistor. Post-layout simulations of a 0.18- $\mu $ m CMOS design highlighted low-supply compliance and strong robustness to process-voltage-temperature variations. Specifically, the output voltage of 177 mV exhibits line sensitivity equal to 54 ppm/V in the 0.4-1.8 V supply range, while DC value of the PSR lower than −40 dB is achieved down to 0.28-V supply. Simulated current consumption is equal to 223 pA, while the mean temperature coefficient is equal to 24.44 ppm/ $\circ $ C from $- 20~\circ $ C to $80~\circ $ C. A compact area footprint of only $115.2~\mu $ m2 is also attained. These results highlight potentialities of the proposed topology for implementations of stable low-voltage and low-power VRs.