A Sub-70-mV SRAM Based on DTMOS Schmitt-Trigger Circuits in 130-nm SOI CMOS for Self-Powered IoT

This paper presents a robust dual-port Static Random Access Memory (SRAM) architecture capable of operating at a sub-70 mV supply voltage. The proposed design employs Dynamic-threshold Schmitt-Trigger (DST) circuits to overcome the challenges of ultra-low-voltage operation. By combining the advantages of Dynamic Threshold MOS (DTMOS) and Schmitt-Trigger (ST) principles, DST enhances the $I_{on}/I_{off}$ ratio and significantly improves tolerance against process variations and device mismatch, enabling reliable operation at ultra-low supply voltages. SRAM arrays of multiple capacities were implemented using DST circuits in a commercial 130 nm SOI CMOS technology. The design employs a D-latch storage cell to reduce area and power consumption. The proposed SRAM features dedicated write and read paths with hierarchical decoders, whereas a multiplexer-based readout approach results in a regular and compact layout. Post-layout Monte Carlo simulations incorporating $\pm {\,}6{\,}\sigma $ process variations and mismatch demonstrate reliable operation at a supply voltage of 65 mV, which is substantially lower than previously reported state-of-the-art ultra-low voltage SRAM designs. At 65 mV, a 0.5 kb SRAM array achieves a read access energy of 1.8 pJ/bit at 2.2 kHz and a leakage power of 404 pW/bit.