A Timing-Driven Hierarchical Macro Placement Framework for Large-Scale Complex IP Blocks

Asia and South Pacific Design Automation Conference (ASP-DAC) 2026

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Authors: Wei Fu, Lixin Chen, Jinghui Zhou, Ziran Zhu
DOI: 10.1109/asp-dac66049.2026.11420370
Cited by: 0
References: 13

Fields of Study & Subjects

VLSI and FPGA Design Techniques Embedded Systems Design Techniques Low-power high-performance VLSI design

Publication details

Journal / source
Asia and South Pacific Design Automation Conference (ASP-DAC)
Pages
772–778
Publication date
19 January 2026
Language
EN