H 2 NoC: A Hybrid NoC Architecture for FPGAs with Hardened Interconnects

Modern FPGA platforms with high-bandwidth memory (HBM) subsystems often incorporate hardened interconnects in their static regions to alleviate routing congestion in programmable logic. However, these interconnects typically suffer from up to 67% bandwidth degradation in platforms such as the Alveo U280 under specific access patterns due to their inherent structural limitations. Previous works introduce custom Networks-on-Chip (NoC) in FPGA programmable logic but fail to fully utilize all 32 HBM channels due to excessive resource overhead and severe routing congestion. In this paper, we propose $\mathbf{H}^{2} \mathbf{N o C}$, a hybrid NoC architecture that integrates the hardened interconnect embedded in the static HBM region with a custom Butterfly-Fat Tree (BFT) NoC in programmable logic, enabling full 32-channel utilization with minimum routing congestion. The custom 3-stage NoC is partitioned into four clusters, enabling flexible floorplanning strategies that facilitate optimal implementation across SLRs. To compensate for the reduced number of on-chip stages, an out-of-order generating buffer (OGB) is incorporated, which utilizes lightweight AXI reordering to mitigate read-bandwidth degradation. Compared to prior state-of-the-art NoCs on Alveo series, $\mathbf{H}^{\mathbf{2}} \mathbf{N o C}$ demonstrates an improvement of 134.8% in bandwidth-to-resource efficiency. $\mathrm{H}^{2} \mathrm{NoC}$ is evaluated using a set of synthetic benchmarks designed to emulate various traffic patterns. It achieves a peak bandwidth of $391 \mathrm{~GB} / \mathrm{s}$ under bit permutation traffic and sustains over $200 \mathrm{~GB} / \mathrm{s}$ across most traffic patterns. The proposed hybrid architecture delivers performance comparable to a full custom 5-stage BFT network while requiring significantly fewer FPGA resources.