A Relaxation Oscillator with 2.93μJ/cycle Energy Efficiency and 0.068% Period Jitter

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Authors: Yongjuan Shi, Xun Liu, Chen Hu, Xiyuan Tang, Junmin Jiang
Cited by: 0
References: 10

Abstract

This paper presents a $\mathbf{2 M H z}$ relaxation oscillator (ROSC) designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (C-FIA) is adopted such that (1) the requirement of comparator speed is significantly alleviated and (2) the power consumption of the amplifier is further reduced. The proposed ROSC was fabricated in a 180 nm CMOS process and occupies only $0.1 \mathrm{~mm}^{2}$ active area. The measurement results with 8 samples show that the average power consumption is only $2.93 \mu \mathrm{~J} /$ cycle $(\mu \mathrm{W} / \mathrm{MHz})$ at 1 V supply voltage at room temperature. The average standard variation of the period jitter is 345 ps, which is as low as 0.068% of the 500 ns typical oscillation period (Tosc).

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Radio Frequency Integrated Circuit Design Low-power high-performance VLSI design

Publication details

Journal / source
Asia and South Pacific Design Automation Conference (ASP-DAC)
Pages
230–232
Publication date
19 January 2026
Language
EN